[VHDL] Attributes | 속성

Attributes

속성

- 코드의 수정을 용이하게 한다.
- Index에 대한 Alias 기능을 제공한다.

* Predefined Attributes
- Value Kind
- Function Kind
- Signal Kind
- Type Kind
- Range Kind

Attribute	Description
S'event	Signal S에 Event가 발생되었는지에 대한 여부 (true/false)
S'last_event	Signal S의 마지막 Event가 발생한 후 경과한 시간값
S'active	Signal S가 변경되었는지에 대한 여부 (true/false)
S'last_active	Signal S가 마지막으로 변경된 후 경과한 시간값
S'last_value	Signal S에 마지막 Event가 발생하기 이전의 값

Example. Attribute Usage

IF (clock = '1' AND clock'event) THEN
    ASSERT(d'last_event >= 10ns) REPORT "Setup violation error";

Example. Attribute Usage

IF (clock = '1' AND clock'event) THEN
    -- Clock Rising Edge
    
IF (clock = '0' AND clock'event) THEN
    -- Clock Falling Edge

Value Kind Attribute

1) Value Type Attribute

t'left	Returns the left bound of type
t'right	Returns the right bound of type
t'high	Returns the upper bound of type
t'low	Returns the lower bound of type

Example. Value Type Attribute

PROCESS(x)
    subtype smallreal IS real range -1.0E6 TO 1.0E6;
    variable q : real;
BEGIN
    q := smallreal'left;  -- Returns -1.0E6
END PROCESS;

Example. Value Type Attribute

PROCESS(x)
    type bit_range IS array(31 DOWNTO 0) OF bit;
    variable left_range, right_range : integer;
    variable high_range, low_range   : integer;
BEGIN
    left_range  := bit_range'left;   -- Returns 31
    right_range := bit_range'right;  -- Returns 0
    high_range  := bit_range'high;   -- Returns 31
    low_range   := bit_range'low;    -- Returns 0
END PROCESS;

Example. Value Type Attribute

ARCHITECTURE b OF a IS
    TYPE color IS (blue, black, green, yellow, red);
    SUBTYPE r_color IS color RANGE red DOWNTO green; -- High (red, yellow, green) Low
    SIGNAL c1, c2, c3, c4, c5, c6, c7, c8 : color;
BEGIN
    c1 <= color'left;     -- Returns blue
    c2 <= color'right;    -- Returns red
    c3 <= color'high;     -- Returns red
    c4 <= color'low;      -- Returns blue
    
    c5 <= r_color'left;   -- Returns red
    c6 <= r_color'right;  -- Returns green
    c7 <= r_color'high;   -- Returns red
    c8 <= r_color'low;    -- Returns green
END b;

2) Value Array Attribute

a'length

Returns the total length of the array range

Example. Value Array Attribute

PROCESS(x)
    TYPE bit4 IS array(0 TO 3) OF bit;
    TYPE bit_strange IS array(10 TO 20) OF bit;
    VARIABLE len1, len2 : integer;
BEGIN
    len1 := bit4'length;         -- Returns 4
    len2 := bit_strange'length;  -- Returns 11
END PROCESS;

3) Value Block Attribute

b'behavior	Returns true if the block specified by the block label or architecture specified by the architecture name contains no component instantiation statements.
b'structure	Returns true if the block or architecture contains only component instantiation statements and/or passive processes.

Example. Value Block Attributes

USE work.std_logic_1164.all'

ENTITY shifter IS
    PORT( clk, left : IN std_logic;
            right : OUT std_logic );
END shifter;

ARCHITECTURE structural OF shifter IS
    COMPONENT dff
        PORT( d, clk : IN  std_logic;
                   q : OUT std_logic );
    END COMPONENT;
    
    SIGNAL i1, i2, i3 : std_logic;
BEGIN
    u1 : dff PORT MAP(d => left, clk => clk, q => i1);
    u2 : dff PORT MAP(d => i1,   clk => clk, q => i2);
    u3 : dff PORT MAP(d => i2,   clk => clk, q => i3);
    u4 : dff PORT MAP(d => i3,   clk => clk, q => right);
    checktime : PROCESS(clk) -- No signal assignment
        VARIABLE last_time : time := time'left;
    BEGIN
        assert(now - last_time >= 20ns)
            REPORT "Spike on clock" SEVERITY warning;
        last_time := now;
    END PROCESS checktime;
END structural;

-- structural'structure -> Returns true
-- structural'behavior  -> Returns false

Function Kind Attribute

1) Function Type Attribute
- Return type values.

t'pos (x)	Returns position from value in type
t'val (x)	Returns value from position in type
t'succ (x)	Returns next value in type
t'pred (x)	Returns previous value in type
t'leftof (x)	Returns left value in type
t'rightof (x)	Returns right value in type

* Ascending Range (ex. 0 to 7)
t'succ(x) = t'rightof(x)
t'pred(x) = t'leftof(x)

* Descending Range (ex. 7 downto 0)
t'succ(x) = t'leftof(x)
t'pred(x) = t'rightof(x)

Example. Function Type Attributes

TYPE color IS (red, yellow, green, blue, purple, black);

color'succ(blue)     -- Return purple
color'pred(green)    -- Return yellow
color'rightof(blue)  -- Return purple
color'leftof(green)  -- Return yellow

color'pred(red)      -- Runtime Error

2) Function Array Attribute
- Return array bounds.

a'left	Returns the left boud of array
a'right	Returns the right bound of array
a'high	Returns the upper bound of array
a'low	Returns the lower bound of array

* Ascending Range (ex. 0 to 7)
a'left = a'low
a'right = a'high

* Descending Range (ex. 7 downto 0)
a'left = a'high
a'right = a'low

Example. Function Array Attributes

TYPE ram_data_type IS array (0 TO 511) OF integer;
    ...
PROCESS(cs, addr, rw)
    VARIABLE ram_data : ram_data_type;
    VARIABLE ram_init : boolean := false;
BEGIN
    IF NOT(ram_init) THEN
        FOR i IN ram_data'low TO ram_data'high LOOP
            ram_data(i) := 0;
        END LOOP;
        ram_init := true;
    END IF;
    ...
END PROCESS;

3) Function Signal Attribute
- Return signal history.

a'event	Returns if an event occurred (값의 변화를 감지) (값이 변해야 true)
a'active	Returns if an activity occurred (회로 자체가 동작하고 있는지를 감지) (값이 바뀌지 않아도 true)
a'last_event	Returns time since previous event
a'last_active	Returns time since previous activity
a'last_value	Returns previous value

Example. Function Signal Attributes

USE work.std_logic_1164.all;

ENTITY dff IS
    GENERIC(setup_time : time := 0.7ns);
    PORT( d, clk : IN  std_logic;
               q : OUT std_logic );
END dff;

ARCHITECTURE attr_test OF dff IS
BEGIN
    PROCESS(clk)
    BEGIN
        If (clk = '1' AND clk'event AND clk'last_value = '0') THEN
            ASSERT(d'last_event >= setup_time)
                REPORT "Setup violation"
                SEVERITY error;
            q <= d;
        END IF;
    END PROCESS;
END attr_test;

Signal Kind Attribute

s'delayed [(time)]	Creates a signal of the same type as the reference signal that follows the reference signal, delayed by the time.
s'stable [(time)]	Creates a boolean signal that is true whenever the reference signal has had no events for the time - event와 반대되는 개념
s'quite [(time)]	Creates a boolean signal that is true whenever the reference signal has had no transactions(activities) or events for the time - active와 반대되는 개념
s'transaction	Creates a signal of type bit that toggles its value for every transaction or event that occurs on s

Example. Signal Kind Attributes

USE work.std_logic_1164.all;

ENTITY and2 IS
    GENERIC(a_ipd, b_ipd, c_opd : time);
    PORT( a, b : IN  std_logic;
             c : OUT std_logic );
END and2;

ARCHITECTURE trans OF and2 IS
    SIGNAL inta, intb : std_logic;
BEGIN
    inta <= TRANSPORT a AFTER a_ipd;
    intb <= TRANSPORT b AFTER b_ipd;
    c    <= inta AND intb AFTER c_opd;
END trans;

ARCHITECTURE attr OF and2 IS
BEGIN
    c <= a'delayed(a_ipd) AND b'delayed(b_ipd)
        AFTER c_opd;
END attr;

* TRANSPORT : 내부 Delay Time이 기준 Delay Time보다 작은 데이터도 무시하지 않는다.
* INTERNAL : 내부 Delay Time이 기준 Delay Time보다 작은 데이터를 무시한다.

Example. Signal Kind Attributes

hold_check : PROCESS(clk'delayed(hold_time))
BEGIN
    IF (clk'delayed(hold_time) = '1') AND clk'delayed(hold_time)'event) THEN
        ASSERT(d'last_event = 0ns) OR (d'last_event >= hold_time)
            REPORT "Hold violation"
            SEVERITY error;
    END IF;
END PROCESS hold_check;

Example. Signal Kind Attributes

USE work.std_logic_1164.all;

ENTITY pulse_gen IS
    PORT( a : IN  std_logic;
          b : OUT boolean );
END pulse_gen;

ARCHITECTURE attr OF pulse_gen IS
BEGIN
    b <= a'stable(10ns);
END attr;

Type Kind Attribute

t'base

Returns the base type

* Base Type <-> Sub Type

Example. Type Kind Attributes

do_nothing : PROCESS(x)
    TYPE color IS (red, blue, green, yellow, brown);
    SUBTYPE color_sub IS color RANGE red TO green;
    VARIABLE a : color;
BEGIN
    a := color_sub'base'right;         -- a = brown
    a := color'base'left;              -- a = red
    a := color_sub'base'succ(green);   -- a = yellow
END PROCESS do_nothing;

Range Kind Attribute

a'range	Returns the range
a'reverse_range	Return the reverse range

Example. Range Kind Attributes

FUNCTION vec_to_int (s : bit_vector) RETURN integer IS
    VARIABLE result : integer := 0;
BEGIN
    FOR i IN s'range LOOP
        result := result * 2;
        IF (s(i) = '1') THEN
            result := result + 1;
        END IF;
    END LOOP;
    RETURN result;
END vec_to_int;

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[VHDL] Attributes | 속성

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