[VHDL] Flip Flop Modeling | 플립플롭 모델링

Flip Flop Modeling

플립플롭 모델링

* Flip Flop (URL)

---

RS Flip Flop Implementation

LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    
ENTITY ff_rs IS
    PORT( clock : IN  std_logic;
           R, S : IN  std_logic;
              Q : OUT std_logic );
END ff_rs;

ARCHITECTURE design OF ff_rs IS
signal q_tmp : std_logic;

BEGIN
    PROCESS(clock)
    BEGIN
        IF (clock'event AND clock = '1') THEN
            
            IF (S = '0' AND R = '0') THEN
                q_tmp <= q_tmp;
            ELSIF (S = '0' AND R = '1') THEN
                q_tmp <= '0';
            ELSIF (S = '1' AND R = '0') THEN
                q_tmp <= '1';
            ELSE
                q_tmp <= '-';
            END IF;
        END IF;
    END PROCESS;
    
    Q <= q_tmp;
END design;

---

D Flip Flop Implementation

LIBRARY ieee;
    USE ieee.std_logic_1164.all;

ENTITY ff_d IS
    PORT( clock : IN  std_logic;
          D     : IN  std_logic;
          Q     : OUT std_logic );
END ff_d;

ARCHITECTURE design OF ff_d IS
signal q_tmp : std_logic;
BEGIN
    PROCESS(clock)
    BEGIN
        IF( clock'event AND clock = '1' ) THEN
            q_tmp <= D;
        ELSE
            q_tmp <= q_tmp;
        END IF;
    END PROCESS;
    
    Q <= q_tmp;
END design;

---

T Flip Flop Implementation

LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    
ENTITY ff_t IS
    PORT( clock : IN  std_logic;
              T : IN  std_logic;
              Q : OUT std_logic );
END ff_t;

ARCHITECTURE design OF ff_t IS
signal q_tmp : std_logic;
BEGIN
    PROCESS(clock)
    BEGIN
        IF( clock'event AND clock = '1') THEN
            IF( T = '1' ) THEN
                q_tmp <= NOT q_tmp;
            ELSE
                q_tmp <= q_tmp;
            END IF;
        END IF;
    END PROCESS;
    
    Q <= q_tmp;
END design;

---

JK Flip Flop Implementation

LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    
ENTITY ff_jk IS
    PORT( clock : IN  std_logic;
          J, K  : IN  std_logic;
          Q     : OUT std_logic );
END ff_jk;

ARCHITECTURE design OF ff_jk IS
signal q_tmp : std_logic;
BEGIN
    PROCESS(clock)
    BEGIN
        IF( clock'event AND clock = '1') THEN
            IF( J = '0' AND K = '0' ) THEN
                q_tmp <= q_tmp;
            ELSIF ( J = '0' AND K = '1' ) THEN
                q_tmp <= 0;
            ELSIF ( J = '1' AND K = '0' ) THEN
                q_tmp <= 1
            ELSE
                q_tmp <= NOT q_tmp;
            END IF;
        END IF;
    END PROCESS;
    
    Q <= q_tmp;
END design;