[VHDL] Synchronous Reset and Asynchronous Reset | 동기 Reset과 비동기 Reset

Synchronous Reset and Asynchronous Reset

동기 Reset과 비동기 Reset

* Synchronous : Clock Signal에 의존적
* Asynchronous : Clock Signal에 독립적

* D Flip Flop Implementation

LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    
ENTITY ff_d IS
    PORT( clock : IN  std_logic;
              D : IN  std_logic;
              Q : OUT std_logic );
END ff_d;

ARCHITECTURE design OF ff_d IS
SIGNAL q_tmp : std_logic;
BEGIN
    PROCESS(clock)
    BEGIN
        IF (clock'event AND clock = '1') THEN
            q_tmp <= D;
        ELSE
            q_tmp <= q_tmp;
        END IF
    END PROCESS;
    Q <= q_tmp;
END design;

---

Asynchronous Reset

1) Using D FFs

LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    
ENTITY ff_d_async IS
    PORT( clock : IN  std_logic;
          reset : IN  std_logic;
              D : IN  std_logic;
              Q : OUT std_logic );
END ff_d_async;

ARCHITECTURE design OF ff_d_async IS
BEGIN
    PROCESS(clock, reset)
    BEGIN
        IF (reset = '1') THEN
            Q <= '0';
        ELSIF (clock'event AND clock = '1') THEN
            Q <= D;
        END IF
    END PROCESS;
END design;

2) Using T FFs

LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    
ENTITY ff_t IS
    PORT( clock : IN  std_logic;
              T : IN  std_logic;
              Q : OUT std_logic );
END ff_t;

ARCHITECTURE design OF ff_t IS
SIGNAL q_tmp : std_logic;
BEGIN
    PROCESS(clock)
    BEGIN
        IF (reset = '0') THEN
            q_tmp <= '0';
        ELSIF (clock'event AND clock = '1') THEN
            IF (T = '1') THEN
                q_tmp <= NOT q_tmp;
            ELSE
                q_tmp <= q_tmp;
            END IF;
        END IF;
    END PROCESS;
    Q <= q_tmp;
END design;  

---

Synchronous Reset

1) Using D FFs

LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    
ENTITY ff_d_sync IS
    PORT( clock : IN  std_logic;
          reset : IN  std_logic;
              D : IN  std_logic;
              Q : OUT std_logic );
END ff_d_sync;

ARCHITECTURE design OF ff_d_sync Is
BEGIN
    PROCESS(clock, reset)
    BEGIN
        If (clock'event AND clock = '1') THEN
            If (reset = '1') THEN
                Q <= '0';
            ELSE
                Q <= D;
            END IF;
        END IF;
    END PROCESS;
END design;

2) Using T FFs

LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    
ENTITY ff_t IS
    PORT( clock : IN  std_logic;
              T : IN  std_logic;
              Q : OUT std_logic );
END ff_t;

ARCHITECTURE design OF ff_t IS
SIGNAL q_tmp : std_logic;
BEGIN
    PROCESS(clock)
    BEGIN
        IF (clock'event AND clock = '1') THEN
            IF (reset = '1') THEN
                q_tmp <= '0';
            ELSIF (T = '1') THEN
                q_tmp <= NOT q_tmp;
            ELSE
                q_tmp <= q_tmp;
            END IF;
        END IF;
    END PROCESS;
    Q <= q_tmp;
END design;