[VHDL] Generic | 제네릭

Generic

제네릭

- Entity Instance에 Parameter를 전달할 수 있게 하는 Mechanism이다.
- Parameter로는 Propagation Delay, Load Capacitance, Resistance, Data-Path Widths, Signal Widths 등이 될 수 있다.
ex) generic을 이용하여 VHDL 코드 상에서 n-Bit Adder를 구현할 수 있다.

- 제네릭은 코드의 가독성(독해성)을 제고한다.
- 코드의 유지 보수를 용이하게 한다.

Example. Generic Declaration

ENTITY nbit_adder IS
    GENERIC (bits : integer);
    PORT( a, b : IN  std_logic_vector(bits-1 DOWNTO 0);
             c : OUT std_logic_vector(bits-1 DOWNTO 0) );
END nbit_adder;

ARCHITECTURE design OF nbit_adder IS
BEGIN
    c <= a + b;
END design;

Example. Circuit involved Generic Statement

ENTITY nbit_adder_tb IS
END nbit_adder_tb;

ARCHITECTURE design OF nbit_adder_tb IS
    COMPONENT nbit_adder
        GENERIC(bits : integer);
        PORT( a, b : IN  std_logic_vector(bits-1 DOWNTO 0);
                 c : OUT std_logic_vector(bits-1 DOWNTO 0) );
    END COMPONENT;
    ...
BEGIN
    U_NBIT_ADDER : nbit_adder
        GENERIC MAP (bits => 8);    -- 8 Bits Adder
        PORT MAP ( a => a, b => b, c => c);
    ...
END design;

Example. Delay Using Generic

USE work.std_logic_1164.all;
ENTITY and2 IS
    GENERIC (delay : time := 1ns);
    PORT ( a, b : IN  std_logic;
              c : OUT std_logic );
END and2;

ARCHITECTURE constant_delay OF and2 IS
BEGIN
    c <= a AND b AFTER delay;
END constant_delay;

Example. Generics

USE work.std_logic_1164.all;

ENTITY and2 IS
    GENERIC (rise, fall : time;
                   load : integer );
    PORT (a, b : IN  std_logic;
             c : OUT std_logic );
END and2;

ARCHITECTURE load_dependent OF and2 IS
    SIGNAL internal : std_logic;
BEGIN
    internal <= a AND b;
    c <= internal AFTER (rise + load * 2ns) WHEN internal = '1' ELSE
         internal AFTER (fall + load * 3ns);
END load_dependent;   

ENTITY test IS
    PORT( ina, inb, inc, ind : IN  std_logic;
                  out1, out2 : OUT std_logic );
END test;

ARCHITECTURE test_arch OF test IS
    COMPONENT and2
        GENERIC( rise, fall : time;
                       load : integer );
        PORT( a, b : IN  std_logic;
                 c : OUT std_logic );
    END COMPONENT;
BEGIN
    u1 : and2
        GENERIC MAP( 10ns, 12ns, 3 );
        PORT MAP( ina, inb, out1 );
    u2 : and2
        GENERIC MAP( 9ns, 11ns, 5 );
        PORT MAP( inc, ind, out2 );
END test_arch;

-- Default Value for Generics
ARCHITECTURE test_arch OF test IS
    COMPONENT and2
        GENERIC( rise, fall : time := 10ns;
                       load : integer := 0 );
        PORT( a, b : IN  std_logic;
                 c : OUT std_logic );
    END COMPONENT;
BEGIN
    u1 : and2
        GENERIC MAP( 10ns, 12ns, 3 );
        PORT MAP( ina, inb, out1 );
    u2 : and2
        GENERIC MAP( 9ns, 11ns, 5 );
        PORT MAP( inc, ind, out2 );
END test_arch;

Example. 2 to 4 Decoder Using Generics

USE work.std_logic_1164.all;

ENTITY decode IS
    PORT( a, b, en       : IN  std_logic;
          q0, q1, q2, q3 : OUT std_logic );
END decode;

CONFIGURATION decode_map_con OF decode IS
    FOR structural
        FOR i1 : inv
            USE ENTITY work.inv(behave);
            PORT MAP( a => x, b => y );
        END FOR;
        
        FOR i2 : struc_inv
            USE CONFIGURATION work.inv_transcon;
            PORT MAP( a => i1, b => o1 );
        END FOR;
        
        FOR all : and3
            USE ENTITY work.and3(behave);
        END FOR;
    END FOR;
END decode_map_con;

Example. Generic Value Specifications in the Generic Declaration

USE work.std_logic_1164.all;

PACKAGE p_time_pack IS
    TYPE t_time_mode IS (min, typ, max);
    
    TYPE t_rise_fall IS record
        rise : time;
        fall : time;
    END record;
    
    TYPE t_time_rec IS array(t_time_mode'low TO t_time_mode'high) OF t_rise_fall;
    
    FUNCTION calc_delay( newstate : std_logic;
                             mode : t_time_mode;
                         delaytab : t_time_rec )
    RETURN time;
END p_time_pack;

PACKAGE BODY p_time_pack Is
    FUNCTION calc_delay ( newstate : std_logic;
                          mode     : t_time_mode;
                          delaytab : t_time_rec )
    RETURN time IS
    BEGIN
        CASE newstate IS
            WHEN '0' => RETURN delaytab (mode).fall;
            WHEN '1' => RETURN delaytab (mode).rise;
            WHEN OTHERS =>
                IF (delaytab (mode).rise <= delaytab (mode).fall) THEN
                    RETURN delaytab (mode).rise;
                ELSE
                    RETURN delaytab (mode).fall;
                END IF;
        END CASE;
    END calc_delay;
END p_time_pack;

Example. Inverter Using Generics and p_time_pack package (User-defined package)

USE work.std_logic_1164.all;
USE work.p_time_pack.all;

ENTITY inv IS
    GENERIC( mode     : t_time_mode;
        	 delaytab : t_time_rec := ( (1ns, 2ns),
                                        (2ns, 3ns),
                                        (3ns, 4ns) );
    PORT( a : IN  std_logic;
          b : OUT std_logic );
END inv;

ARCHITECTURE inv_gen OF inv IS
BEGIN
    inv_proc : PROCESS(a)
        VARIABLE state : std_logic;
    BEGIN
        state := NOT(a);
        b <= state AFTER calc_delay(state, mode, delaytab);
    END PROCESS inv_proc;
END inv_gen;

Example. AND Gate Using Generics and p_time_pack package (User-defined package)

USE work.std_logic_1164.all;
USE work.p_time_pack.all;

ENTITY and3 IS
    GENERIC( mode     : t_time_mode;
             delaytab : t_time_rec := ( (2ns, 3ns),
                                        (3ns, 4ns),
                                        (4ns, 5ns) );
    PORT MAP( a1, a2, a3 : IN  std_logic;
                      o1 : OUT std_logic );
END and3;

ARCHITECTURE and3_gen OF and3 IS
BEGIN
    and3_proc : PROCESS(a1, a2, a3)
        VARIABLE state : std_logic;
    BEGIN
        state := a1 AND a2 AND a3;
        o1 <= state AFTER calc_delay(state, mode, delaytab);
    END PROCESS and3_proc;
END and3_gen;

Example. Decoder Using Generics

ARCHITECTURE structural OF decode IS
    COMPONENT inv
        GENERIC( mode : t_time_mode;
                 delaytab : t_time_rec );
        PORT( a : IN  std_logic;
              b : OUT std_logic );
    END COMPONENT;
    
    COMPONENT and3
        GENERIC( mode     : t_time_mode;
                 delaytab : t_time_rec );
        PORT( a1, a2, a3 : IN  std_logic;
                      o1 : OUT std_logic );
    END COMPONENT;
    SIGNAL nota, notb : std_logic;
BEGIN
    i1 : inv
        GENERIC MAP( mode => max, delaytab => ( (1.3ns, 1.9ns), (2.1ns, 2.9ns), (3.2ns, 4.1ns) ) );
        PORT MAP( a, nota );
        
    i2 : inv
        GENERIC MAP( mode => min, delaytab => ( (1.3ns, 1.9ns), (2.1ns, 2.9ns), (3.2ns, 4.1ns) ) );
        PORT MAP( b, notb );
        
    a1 : and3
        GENERIC MAP( mode => typ, delaytab => ( (1.3ns, 1.9ns), (2.1ns, 2.9ns), (3.2ns, 4.1ns) ) );
        PORT MAP( nota, en, notb, q0 );

    a2 : and3
        GENERIC MAP( mode => min, delaytab => ( (1.3ns, 1.9ns), (2.1ns, 2.9ns), (3.2ns, 4.1ns) ) );
        PORT MAP( a, en, notb, q1 );
        
    a3 : and3
        GENERIC MAP( mode => max, delaytab => ( (1.3ns, 1.9ns), (2.1ns, 2.9ns), (3.2ns, 4.1ns) ) );
        PORT MAP( nota, en, b, q2 );
        
    a4 : and3
        GENERIC MAP( mode => max, delaytab => ( (2.3ns, 2.9ns), (3.1ns, 3.9ns), (4.2ns, 5.1ns) ) );
        PORT MAP( a, en, b, q3 );
END structural;

Example. Generics and Configuration

USE work.std_logic_1164.all;

ENTITY and3 IS
    GENERIC( int_rise, int_fall : time;
             ext_rise, ext_fall : time );
    PORT( a1, a2, a3 : IN  std_logic;
                  o1 : OUT std_logic );
END and3;

ARCHITECTURE and3_gen1 OF and3 IS
BEGIN
    and3_proc : PROCESS (a1, a2, a3)
        VARIABLE state : std_logic;
    BEGIN
        state := a1 AND a2 AND a3;
        IF (state = '1') THEN
            o1 <= state AFTER (int_rise + ext_rise);
        ELSIF (state = '0') THEN
            o1 <= state AFTER (int_fall + ext_fall);
        ELSE
            o1 <= state AFTER (int_fall + ext_fall);
        END IF;
    END PROCESS and3_proc;
END and3_gen1;

-- Decoder Implementation
ENTITY decode IS
    PORT( a, b, en       : IN  std_logic;
          q0, q1, q2, q3 : OUT std_logic );
END decode;

ARCHITECTURE structural OF decode IS
    COMPONENT inv
        PORT( a : IN  std_logic;
              b : OUt std_logic );
    END COMPONENT;
    
    COMPONENT and3
        PORT( a1, a2, a3 : IN  std_logic;
                      o1 : OUT std_logic );
    END COMPONENT;
    
    SIGNAL nota, notb : std_logic;
BEGIN
    i1 : inv PORT MAP (a, nota);
    i2 : inv PORT MAP (b, notb);
    a1 : and3 PORT MAP (nota, en, notb, q0);
    a2 : and3 PORT MAP (a, en, notb, q1);
    a3 : and3 PORT MAP (nota, en, b, q2);
    a4 : and3 PORT MAP (a, en, b, q3);
END structural;

CONFIGURATION decode_gen1_con OF decode IS
    FOR structural
        FOR i1 : inv
            USE ENTITY work.inv(inv_gen1)
            GENERIC MAP( int_rise => 1.2ns, int_fall => 1.7ns, ext_rise => 2.6ns, ext_fall => 2.5ns);
        END FOR;
        FOR i2 : inv
            USE ENTITY work.inv(inv_gen1)
            GENERIC MAP( int_rise => 1.2ns, int_fall => 1.7ns, ext_rise => 2.8ns, ext_fall => 2.9ns);
        END FOR;
        FOR a1 : and3
            USE ENTITY work.and3(and3_gen1)
            GENERIC MAP( int_rise => 2.2ns, int_fall => 2.7ns, ext_rise => 3.6ns, ext_fall => 3.5ns);
        END FOR;
        FOR a2 : and3
            USE ENTITY work.and3(and3_gen1)
            GENERIC MAP( int_rise => 2.2ns, int_fall => 2.7ns, ext_rise => 3.1ns, ext_fall => 3.2ns);
        END FOR;
        FOR a3 : and3
            USE ENTITY work.and3(and3_gen1)
            GENERIC MAP( int_rise => 2.2ns, int_fall => 2.7ns, ext_rise => 3.3ns, ext_fall => 3.4ns);
        END FOR;
        FOR a4 : and3
            USE ENTITY work.and3(and3_gen1)
            GENERIC MAP( int_rise => 2.2ns, int_fall => 2.7ns, ext_rise => 3.0ns, ext_fall => 3.1ns);
        END FOR;
    END FOR;
END decode_gen1_con;