[VHDL] VHDL Operator | VHDL 연산자

VHDL Operator

VHDL 연산자

* Priority

Priority	Operator
	Logical Operator	or, and, nor, nand, xor, xnor
High	Relational Operator	=, /=, >, <, >=, <=
	Adding Operator	+, -, & (Concatenation)
	Unary Operator	+, - (Sign)
	Multiplying	*, /, mod, rem
Low	Etc	**, abs, not

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Logical Operator

not
and
or
nand
nor
xor
xnor

Relational Operator

=
/=
<
<=
>
>=

Shift Operator

sll
srl
sla
sra
rol
ror

Adding Operator

+
-
& (Concatenation Op)

ex) ('0', '1', '1') & ('0', 'Z', '1') = ('0', '1', '1', '0', 'Z', '1')

Signing Operator

+
-

Multiplying Operator

*
/
mod (Modulo 연산)
rem (나머지 연산)

Miscellaneous Operator

** (Exponentiation Op)
abs (Absolute Value Op)

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Example Codes

Example. Adder (Data Flow)

LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    
ENTITY adder IS
    PORT( a, b : IN  std_logic_vector(7 DOWNTO 0);
             c : OUT std_logic_vector(7 DOWNTO 0) );
END adder;

ARCHITECTURE data_flow OF adder IS
BEGIN
    c <= a + b;
END data_flow;

Example. Adder & Substracter & Multiplier (Data Flow)

LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    USE ieee.std_logic_unsigned.all;
    
ENTITY alu_arith IS
    PORT( a, b     : IN  std_logic_vector(3 DOWNTO 0);
          add, sub : OUT std_logic_vector(3 DOWNTO 0);
          mul      : OUT std_logic_vecotr(7 DOWNTO 0) );
END alu_arith;

ARCHITECTURE data_flow OF alu_arith IS
BEGIN
    add <= a + b;
    sub <= a - b;
    mul <= a * b;
END data_flow;