[VHDL] Half Adder Modeling | 반가산기 모델링

Half Adder Modeling

반가산기 모델링

- 두 개의 입력 A, B와 두 개의 출력 Carry(C), Sum(S)을 가진다.

* Truth Table for Half Adder

Inputs		Outputs
A	B	S	C
0	0	0	0
0	1	1	0
1	0	1	0
1	1	0	1

* Binary Adder - Half Adder (URL)

---

Half Adder - Behavioral Model

-- Entity Declaration
ENTITY Half_Adder IS
    PORT ( A, B : IN  bit;
     Sum, Carry : OUT bit );
END Half_Adder;

-- Architecture Body
ARCHITECTURE Behavioral_Design of Half_Adder IS
BEGIN
    PROCESS
    BEGIN
        if (A = B) then
            Sum <= '0' after 2 ns;
        else Sum <= '1' after 2 ns;
        end if
        
        if ( (A='1') and (B='1') ) then
            Carry <= '1' after 2 ns;
        else Carry <= '0' after 2 ns;
        end if
        
        wait on A, B;
    END PROCESS
END Behavioral_Design;

---

Half Adder - Dataflow Model

-- Entity Declaration
ENTITY Half_Adder IS
    PORT ( A, B : IN bit;
     Sum, Carry : OUT bit );
END Half_Adder;

-- Architecture Body
ARCHITECTURE Dataflow_Design OF Half_Adder IS
BEGIN
    Sum <= A xor B after 2 ns;
    Carry <= A and B after 2 ns;
END Dataflow_Design;

- \(\texttt{ARCHITECTURE}\)문 내부는 \(\texttt{A}\) 혹은 \(\texttt{B}\)에 Event가 발생되면 Concurrent하게 수행된다.
  (\(\texttt{PROCESS}\)문이 없어서 Sequential하게 수행되지 않음에 유의하자.)