[VHDL] Simple Logic Circuit Modeling

Simple Logic Circuit Modeling

아래 회로를 VHDL로 작성하라.

* Truth Table

Inputs			Output
A	B	C	O
0	0	0	0
0	0	1	0
0	1	0	1
0	1	1	0
1	0	0	0
1	0	1	1
1	1	0	1
1	1	1	1

\(O = \sum\limits (2, 5, 6, 7)\)
\(\quad= A'BC + AB'C + ABC' + ABC\)
\(\quad= AC + BC'\)

---

Behavioral VHDL

-- Entity Body
ENTITY Logic_Gate IS
    PORT ( A, B, C : IN bit;
                 O : OUT bit );
END Logic_Gate;

-- Architecture Body
ARCHITECTURE Behavioral_Design OF Logic_Gate IS
BEGIN
    PROCESS(A, B, C)
        if ( A='1' and C='1' ) then
            O <= '1' AFTER 2ns;
        elsif ( B='1' and C='0' ) then
            O <= '1' AFTER 2ns;
        else
            O <= '0' AFTER 2ns;
        end if;
    END PROCESS
END Behavioral_Design

---

Structural VHDL

-- Entity Body
ENTITY Logic_Gate IS
    PORT ( A, B, C : IN bit;
                 O : OUT bit );
END Logic_Gate;

-- Architecture Body
ARCHITECTURE Structural_Design OF Logic_Gate IS
    signal t_not, t_ac, t_bc : bit;
    
    component AND_Gate
        PORT( AND_in1, AND_in2 : IN bit;
                       AND_out : OUT bit );
    end component
    
    component OR_Gate
        PORT( OR_in1, OR_in2 : IN bit;
                      OR_out : OUT bit );
    end component
    
    component NOT_Gate
        PORT( NOT_in : IN bit;
             NOT_out : OUT bit );
    component 
    
BEGIN
    NOT1 : NOT_Gate PORT map( C, t_not );
    AND1 : AND_Gate PORT map( A, C, t_ac );
    AND2 : AND_Gate PORT map( t_not, B, t_bc);
    OR1 : OR_Gate PORT map( t_ac, t_bc, O);    
END Structural_Design;

---

Simulation Result

ns	A	B	C	O
0	0	0	0	0
100	0	0	1	0
200	0	1	0	1
300	0	1	1	0
400	1	0	0	0
500	1	0	1	1
600	1	1	0	1
700	1	1	1	1