BCD to 7-Segment Display
Truth Table
| Inputs | Outputs | |||||||||
| w | x | y | z | a | b | c | d | e | f | g |
| 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
| 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
| 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 |
| 0 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 |
| 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 |
| 1 | 0 | 1 | 0 | - | - | - | - | - | - | - |
| 1 | 0 | 1 | 1 | - | - | - | - | - | - | - |
| 1 | 1 | 0 | 0 | - | - | - | - | - | - | - |
| 1 | 1 | 0 | 1 | - | - | - | - | - | - | - |
| 1 | 1 | 1 | 0 | - | - | - | - | - | - | - |
| 1 | 1 | 1 | 1 | - | - | - | - | - | - | - |
- : Don't Care
Data-Flow VHDL 문을 이용한 Behavior Model
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY seven_segment_display IS
PORT ( ins : IN std_logic_vector(3 DOWNTO 0);
outs : OUT std_logic_vector(6 DOWNTO 0) );
END seven_segment_display;
ARCHITECTURE data_flow_7seg OF seven_segment_display IS
BEGIN
out_sequence <= "1111110" WHEN (ins = "0000") ELSE
"0110000" WHEN (ins = "0001") ELSE
"1101101" WHEN (ins = "0010") ELSE
"1111001" WHEN (ins = "0011") ELSE
"0110011" WHEN (ins = "0100") ELSE
"1011011" WHEN (ins = "0101") ELSE
"1011111" WHEN (ins = "0110") ELSE
"1110000" WHEN (ins = "0111") ELSE
"1111111" WHEN (ins = "1000") ELSE
"1110011" WHEN (ins = "1001") ELSE
"-------";
END data_flow_7seg;if절 또는 when절 또는 case문들을 이용한 Behavior Model
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY seven_segment_display IS
PORT ( in_sequence : IN std_logic_vector(3 DOWNTO 0);
out_sequence : OUT std_logic_vector(6 DOWNTO 0) );
END seven_segment_display;
ARCHITECTURE behavior_7seg OF seven_segment_display IS
BEGIN
PROCESS(ins)
BEGIN
CASE ins IS
WHEN "0000" => outs <= "1111110";
WHEN "0001" => outs <= "0110000";
WHEN "0010" => outs <= "1101101";
WHEN "0011" => outs <= "1111001";
WHEN "0100" => outs <= "0110011";
WHEN "0101" => outs <= "1011011";
WHEN "0110" => outs <= "1011111";
WHEN "0111" => outs <= "1110000";
WHEN "1000" => outs <= "1111111";
WHEN "1001" => outs <= "1110011";
WHEN OTHERS => outs <= "-------";
END CASE;
END PROCESS
END behavior_7seg;Components를 이용한 Structural 형태로 작성하시오
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY seven_segment_display IS
PORT ( ins : IN std_logic_vector(3 DOWNTO 0); -- Inputs: a, b, c, d
outs : OUT std_logic_vector(6 DOWNTO 0) );
END seven_segment_display;
ARCHITECTURE structural_7seg OF seven_segment_display IS
SIGNAL b_, c_, d_ : bit;
SIGNAL b_d_, bd, bd_, cd, c_d_, cd_, bc_d, b_c, bc_ : bit;
COMPONENT NOT
PORT (I : IN bit;
O : OUT bit );
END COMPONENT
COMPONENT AND2
PORT (I1, I2 : IN bit;
O : OUT bit );
END COMPONENT
COMPONENT AND3
PORT (I1, I2, I3 : IN bit;
O : OUT bit );
END COMPONENT
COMPONENT OR2
PORT (I1, I2 : IN bit;
O : OUT bit );
END COMPONENT
COMPONENT OR3
PORT (I1, I2 : IN bit;
O : OUT bit );
END COMPONENT
COMPONENT OR4
PORT (I1, I2 : IN bit;
O : OUT bit );
END COMPONENT
COMPONENT OR5
PORT (I1, I2 : IN bit;
O : OUT bit );
END COMPONENT
BEGIN
NOT1 : NOT PORT MAP(ins(2), b_);
NOT2 : NOT PORT MAP(ins(1), c_);
NOT3 : NOT PORT MAP(ins(0), d_);
AND1 : AND2 PORT MAP(b_, d_, b_d_);
AND2 : AND2 PORT MAP(ins(2), ins(0), bd);
AND3 : AND2 PORT MAP(ins(2), d_, bd_);
AND4 : AND2 PORT MAP(ins(1), ins(0), cd);
AND5 : AND2 PORT MAP(c_, d_, c_d_);
AND6 : AND2 PORT MAP(ins(1), d_, cd_);
AND7 : AND3 PORT MAP(ins(2), c_, ins(0), bc_d);
AND8 : AND2 PORT MAP(b_, ins(1), b_c);
AND9 : AND2 PORT MAP(ins(2), c_, bc_);
OR1 : OR4 PORT MAP(ins(3), b_d_, bd, ins(1), outs(6));
OR2 : OR4 PORT MAP(ins(3), b_, cd, c_d_, outs(5));
OR3 : OR3 PORT MAP(ins(2), ins(0), c_d_, outs(4));
OR4 : OR5 PORT MAP(ins(3), b_d_, cd_, bc_d, b_c, outs(3));
OR5 : OR2 PORT MAP(ins(3), cd_, outs(2));
OR6 : OR4 PORT MAP(ins(3), bd_, c_d_, bc_, outs(1));
OR7 : OR4 PORT MAP(ins(3), cd_, b_c, bc_, outs(0));
END structural_7seg;