VHDL Analysis
package cell_library is
component AN2 -- 2 inputs AND
port (A , B : in BIT; Z : out BIT) ;
end component ;
component EO -- 2 inputs XOR
port (A , B : in BIT ; Z : out BIT) ;
end component ;
end cell_library.all
use work.cell_library.all ;
entity VHDL is
port ( A , B , C : in BIT ;
Z : out BIT ) ;
end VHDL ;
architecture VHDL_1 of VHDL is
signal AB : BIT ;
begin
U1 : AN2 port map (A, B, AB) ;
U2 : EO port map (AB, C, Z) ;
end VHDL_1;위 VHDL 코드에 해당되는 회로를 그려라.
| Inputs | Output | ||
| A | B | C | Z |
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 0 |
\(Z = AB \oplus C\\
\quad= ABC' + (A' + B')C\\
\quad= ABC' + A'C + B'C\)
위 VHDL 코드를 Data Flow Statement들을 이용한 Behavioral VHDL로 작성해라.
LIBRARY ieee;
use ieee.std_logic_1164.all;
-- Entity Declaration
entity VHDL is
port ( A , B , C : in BIT ;
Z : out BIT ) ;
end VHDL ;
-- Architecture Body
architecture Behavioral_VHDL of VHDL is
signal I : std_logic_vector (2 downto 0);
BEGIN
I <= A & B & C;
PROCESS(A, B, C)
BEGIN
WITH I SELECT Z <=
'0' WHEN "000",
'0' WHEN "010",
'0' WHEN "100",
'0' WHEN "111",
'1' WHEN OTHERS;
END PROCESS
END Behavioral_VHDL;위 VHDL 코드를 if Statement 또는 when Statement 또는 case Statement들을 이용하여 Behavioral VHDL로 작성해라.
-- Entity Declaration
entity VHDL is
port ( A , B , C : in BIT ;
Z : out BIT ) ;
end VHDL ;
-- Architecture Body
architecture Behavioral_VHDL_If of VHDL is
begin
PROCESS(A, B, C)
if (A = '0') then
if ( (B = '0') and (C = '0') ) then
Z <= '0';
elsif ( (B = '0') and (C = '1') ) then
Z <= '1';
elsif ( (B = '1') and (C = '0') ) then
Z <= '0';
else -- A='0' and B='1' and C='1'
Z <= '1';
end if;
else -- A='1'
if ( (B = '0') and (C = '0') ) then
Z <= '0';
elsif ( (B = '0') and (C = '1') ) then
Z <= '1';
elsif ( (B = '1') and (C = '0') ) then
Z <= '1';
else -- A='1' and B='1' and C='1'
Z <= '0';
end if;
end if;
END PROCESS
end Behavioral_VHDL_If;