[VHDL] Test Bench | 테스트 벤치

Test Bench

테스트 벤치

* Test Bench = Test Harness = Test Fixture
- H/W Model의 기능적 정확성을 검증하기 위한 시뮬레이션 S/W이다.
- VHDL은 테스트 벤치를 작성하기에 적합한 HDL이다.

---

Advantages of Writing a Test Bench in VHDL (VHDL을 통한 테스트 벤치 작성의 장점)

- 특정 Simulation Tool이나, 특정 언어를 배우지 않아도 된다.
- VHDL이 IEEE 표준인 덕에, VHDL로 작성된 Test Bench는 다른 Design Tool로 변환 가능하다.
- VHDL은 다양한 Simulation Semantics를 제공한다.

Example. Clock Waveform Generation

ENTITY clock_gen IS
end clock_gen;

ARCHITECTURE for_test_bench OF clock_gen IS
    SIGNAL ClockFast, ClockMed, ClockSlow : BIT := '0';
BEGIN
    ClockFast <= NOT ClockFast AFTER 10 ns;
    ClockMed <= '1' AFTER 20 ns WHEN ClockMed = '0' ELSE
                '0' AFTER 20 ns;
    PROCESS
    BEGIN
        WAIT FOR 30 ns; ClockSlow <= '1';
        WAIT FOR 30 ns; ClockSlow <= '0';
    END PROCESS;
END for_test_bench;

---

Test Bench Example

ENTITY test_bench IS
END test_bench;

ARCHITECTURE adder OF test_bench IS
    COMPONENT add4
        PORT( A, B : IN bit_vector (3 downto 0);
              Cin  : IN BIT;
              S    : OUT bit_vector(3 downto 0);
              Cout : OUT BIT );
    END COMPONENT;
    
    COMPONENT stimulus
        PORT( A, B : OUT bit_vector(3 downto 0);
              Cout : OUT BIT );
    END COMPONENT;
    
    COMPONENT stimulus
        PORT( A, B : OUT bit_vector(3 downto 0);
              C    : OUT BIT );
    END COMPONENT;
    
    SIGNAL s1, s2, s3 : bit_vector(3 downto 0);
    SIGNAL s4, s5 : BIT;
    
    BEGIN
        u0 : add4     PORT MAP (A => s1, b => s2, Cin => s4, S => s3, Cout => s5);
        u1 : stimulus PORT MAP (A => s1, B => s2, C => s4);
END adder;

ENTITY stimulus IS
    PORT( A, B : OUT bit_vector(3 downto 0);
             C : OUT BIT);
END stimulus;

ARCHITECTURE two_vectors OF stimulus IS
BEGIN
    PROCESS
    BEGIN
        A <= "0101"; B <= "1010"; C <= '0'; WAIT FOR 20 ns;
        A <= "0001"; B <= "1100"; C <= '1'; WAIT FOR 20 ns;
    END PROCESS;
END two_vectors;